Integrators and other types of circuits may need to be reset during operation to avoid entering non-linear or otherwise undesirable operating regimes. For example, an integrator can be used to produce an output that is an integration of a signal at its input. During operation, under certain input conditions the output may rise in magnitude continuously until an amplifier of the integrator is forced into non-linear operation. In this situation, it may be desirable to reset the integrator to allow it to continue integrating from a reset output voltage, thus allowing the amplifier to continue operating in a linear or otherwise desirable regime.
FIG. 1 depicts an integrator circuit 20 having a reset capability. The integrator 20 includes an amplifier 24 connected in a negative feedback configuration, with a feedback capacitor C1 connected between its output and a negative input terminal by two feedback switches SA. In operation, the integrator 20 can integrate an input signal INA to produce an output signal OUTA when the feedback switches SA are closed and the feedback loop is active. If the integrator 20 integrates certain input signals for a relatively long time period, the output signal OUTA may eventually rise to a level that can place devices internal to the amplifier 24 in an operating regime that can produce non-linear or otherwise undesirable behavior. To avoid this, the voltage across the capacitor C1, and thus the output voltage OUTA, can be reset to a known value by first opening the feedback switches SA and then closing two reset switches SB, thereby connecting the feedback capacitor C1 between first and second bias voltages VA, VB to establish a voltage difference VA-VB across the capacitor C1. Subsequently, the reset switches SB can be reopened and the feedback switches SA reclosed to resume integration of the input signal INA. When integrating is resumed, e.g., when the feedback switches SA are again closed, the output OUTA can again represent an integration of the input signal INA, although with an output signal beginning from a reset output signal value.
The integrator reset configuration depicted in FIG. 1, however, can be problematic when employed in multichannel or other embodiments. If a plurality of the depicted integrators 20 are used in parallel, and each of a plurality of feedback capacitors C1 are connected to the first and second bias voltages VA, VB by a plurality of reset switches SB, unpredictable and undesirable reset behavior may result. Each time the feedback capacitor C1 of FIG. 1 is reset, the bias voltages VA, VB may undergo an associated deviation from their values as current is drawn from the bias voltage terminals. This can undesirably alter the value of the voltage imposed on the feedback capacitor C1 during the reset operation, and thereby reduce the accuracy with which the reset is conducted. This effect may be exacerbated in an unpredictable manner in the context of the plurality of integrators 20 where each may or may not reset at the same or different times. If an indeterminate subset of a plurality of the integrators 20 reset at the same time, the total capacitance placed across the bias voltages VA, VB, and thereby the degree of deviation from the reset voltage and the accuracy of the reset operation, may be rendered unpredictable.
Thus, a need exists to implement reset in feedback amplifier circuits in a predictable and accurate manner.